`timescale 1ns / 1ps
/************************************************************\
 **  Copyright (c) 2022-2023 Gonsin, Inc.
 **  All Right Reserved.
 **  Author: http://www.anlogic.com/
 **  Description: sync_block
 **  Rev 1.0
**  Note:对异步输入的data_i，进行clk_i同步处理，两级D触发器更加稳定
\************************************************************/

module sync_block(clk_i, data_i, data_o);
   
parameter [1:0] INITIALISE = 2'b00;

input clk_i;
input data_i;
output data_o;

//内部信号
wire data_sync1_w;

//D 触发器
FD #(
INITIALISE[0]
) data_sync(
.C(clk_i),
.D(data_i),
.Q(data_sync1_w)
);

//D 触发器
FD #(
INITIALISE[0]
) data_sync_reg(
.C(clk_i),
.D(data_sync1_w),
.Q(data_o)
);

endmodule
